superscalar architecture - traduzione in Inglese
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superscalar architecture - traduzione in Inglese

CPU THAT IMPLEMENTS INSTRUCTION-LEVEL PARALLELISM WITHIN A SINGLE PROCESSOR
Superscalar architecture; Superscaler; Super-scalar architecture; Superscalar; Superscalar execution
  • CRAY T3e]] supercomputer with four ''superscalar'' [[Alpha 21164]] processors
  • Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed. (IF = instruction fetch, ID = instruction decode, EX = execute, MEM = memory access, WB = register write-back, ''i'' = instruction number, ''t'' = clock cycle [i.e. time])

superscalar architecture         

общая лексика

суперскалярная архитектура

архитектура процессора с несколькими конвейерами, предусматривающая возможность одновременного выполнения более одной обычной машинной (скалярной) команды, т.е. эти команды запускаются в процессоре на выполнение одновременно и выполняются независимо друг от друга на разных конвейерах. Может применяться как в RISC-, так и в CISC-процессорах. Термин впервые появился в 1987 г

Смотрите также

branch prediction; CPU; ILP; instruction queue; scalar processor; SLIC; system architecture

superscalar processor         

общая лексика

суперскалярный процессор

процессор с суперскалярной архитектурой

Смотрите также

superscalar architecture

superscalar         

общая лексика

SS

суперскалярность

суперскалярный

Смотрите также

superscalar architecture

Definizione

АРХИТЕКТУРА
ы, мн. нет, ж.
1. Строительное искусство, зодчество. Средневековая а.
2. Стиль постройки. А. здания. Архитектурный - относящийся к архитектуре.

Wikipedia

Superscalar processor

A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit.

In Flynn's taxonomy, a single-core superscalar processor is classified as an SISD processor (single instruction stream, single data stream), though a single-core superscalar processor that supports short vector operations could be classified as SIMD (single instruction stream, multiple data streams). A multi-core superscalar processor is classified as an MIMD processor (multiple instruction streams, multiple data streams).

While a superscalar CPU is typically also pipelined, superscalar and pipelining execution are considered different performance enhancement techniques. The former executes multiple instructions in parallel by using multiple execution units, whereas the latter executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):

  • Instructions are issued from a sequential instruction stream
  • The CPU dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
  • The CPU can execute multiple instructions per clock cycle
Traduzione di &#39superscalar architecture&#39 in Russo